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data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 1 smart quad low - side switch features product summary short circuit protection overtemperature protection overvoltage protection 8 bit serial data input and dia g- nostic output (spi protocol) direct parallel control of four channels for pwm applications cascadable with other quad switches low quiescent current c compatible input e lecto s tatic d ischarge (esd) protection green product (rohs compliant) aec qualified application c compatible power switch for 12 v and 24 v applications switch for automotiv e and industrial system solenoids, relays and resistive loads injectors robotic controls general description quad low - side switch in smart power technology (spt) with a s erial p eripheral i nterface (spi) and four open drain dmos output stages. the tle 6220 gp is protected by embedded protection fun c- tions and designed for automotive and industrial applications. the output stages can be controlled d i rect in parallel for pwm applications (injector coils), or through serial control via the spi. therefore the tl e 6220 gp is particularly suitable for e n gine management and powertrain systems. block di a gram supply voltage v s 4.5 ? 5.5 v drain source voltage v ds(az) max 60 v on resistance r on 0.32 w output current (all outp. on equal) i d(nom) 1 a (individually) 3 a p g - dso - 20 fault reset cs output stage output control buffer serial interface spi logic sclk si 8 4 gnd vs so 1 4 in1 in2 in3 in4 out1 out4 prg v bb vs as ch. 1 as ch. 1 as ch. 1 8 gnd normal function scb / overload open load short to ground
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 2 pin description pin configuration (top view) pin symbol function 1 gnd ground 2 in2 input channel 2 3 out 1 power output channel 1 4 vs supply voltage 5 reset reset 6 cs chip select 7 prg program (inputs high or low active) 8 out2 power output channel 2 9 in1 input channel 1 10 gnd ground 11 gnd ground 12 in4 input cha nnel 4 13 out3 power output channel 3 14 fault general fault flag 15 so serial data output 16 sclk serial clock 17 si serial data input 18 out4 power output channel 4 19 in3 input channel 3 20 gnd ground heat slug internally conn ected to ground pins gnd 1 20 gnd in2 2 19 in3 out1 3 18 out4 v s 4 17 si reset 5 16 sclk cs 6 15 so prg 7 14 fault out2 8 13 out3 in1 9 12 in4 gnd 10 11 gnd power so - 20
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 3 maximum ratings for t j = ? 40c to 150c parameter symbol values unit supply voltage v s - 0.3 ... +7 v continuous drain source voltage (out1...out4) v ds 45 v input voltage, all inputs and data lines v in - 0.3 ... + 7 v load dump p rotection v load dump = u p + u s ; u p =13.5 v with automotive injector valve r l = 14 w r i 1 ) =2 w ; t d =400ms; in = low or high with r l = 6.8 w ( i d = 2a) r i =2 w ; t d =400ms; in = low or high v load dump 2 ) 62 52 v operating temperature range storage temperature rang e t j t stg - 40 ... + 150 - 55 ... + 150 c output current per channel (see el. characteristics) i d(lim) i d(lim) min a output current per channel @ t a = 25c (all 4 channels on; mounted on pcb ) 3 ) i d 1 a output clamping energy i d = 1a e as 50 mj power dissipation (dc, mounted on pcb) @ t a = 25c p tot 3 w e lectro s tatic d ischarge voltage (human body model) according to mil std 883d, method 3015.7 and eos/esd assn. standard s5.1 - 1993 v esd 2000 v din humidity category, din 40 040 e iec climatic cate gory, din iec 68 - 1 40/150/56 thermal resistance junction ? case (die soldered on the frame) junction - ambient @ min. footprint junction - ambient @ 6 cm 2 cooling area r thjc r thja 2 50 38 k/w 1 ) r i =internal resistance of the load dump test pulse generator ld200 2 ) v loaddump is s etup without dut connected to the generator per iso 7637 - 1 and din 40 839. 3 ) output current rating so long as maximum junction temperature is not exceeded. at t a = 125 c the output cu r rent has to be calculated using r thja according mounting conditions. pcb with heat pipes, backside 6 cm 2 cooling area minimum footprint
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 4 electrical characteristics parameter and conditions symbol values unit v s = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; reset = h (unless otherwise specified) min typ max 1 . power supply, reset supply voltage 4 v s 4.5 -- 5.5 v supply cu rrent 5 i s -- 1 2 ma minimum reset duration (after a reset all parallel inputs are ored with the spi data bits) t r e set,min 10 s 2 . power outputs on resistance v s = 5 v; i d = 1 a t j = 25c t j = 150c r ds(on) -- -- 0.32 -- 0.4 0.7 w output clampin g voltage output off v ds(az) 45 53 60 v current limit i d(lim) 3 4.5 6 a output leakage current v reset = l i d(lkg) -- -- 10 a turn - on time i d = 1 a, resistive load t on -- 5 10 s turn - off time i d = 1 a, resistive load t off -- 5 10 s 3 . digital inputs input low voltage v inl - 0.3 -- 1.0 v input high voltage v inh 2.0 -- vs+0.3 v input voltage hysteresis v inhys 50 100 200 mv input pull down/up current (in1 ... in4) i in(1..4) 20 50 100 a prg, reset pull up current i in (prg,res) 20 50 100 a input pull down current (si, sclk) i in(si,sclk) 10 20 50 a input pull up current ( cs ) i in(cs) 10 20 50 a 4 . digital outputs (so, fault ) so high state output voltage i soh = 2 ma v soh v s - 0.4 - - -- v so low state output voltage i sol = 2.5 ma v sol -- -- 0.4 v output tri - state leakage current cs = h, 0 v so v s i solkg - 10 0 10 a fault output low voltage i fault = 1.6 ma v faultl -- -- 0.4 v current limitation ; overload threshold current i d(lim) 1...4 3 4.5 6 a overtemperature shutdown threshold hysteresis 6 t th(sd) t hys 170 -- -- 10 200 -- c k 4 for v s < 4.5v the power stages are switched according the input signals and data bits or are definitely switched off. this undervoltage reset gets active at v s = 3v (typ. value) and is guaranteed by design. 5 if reset = l the supply current is reduced to typ. 20a 6 this parameter will not be tested but guaranteed by design
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 5 electrical characteristics cont. parameter and conditions symbol values unit v s = 4.5 to 5.5 v ; t j = - 40 c to + 150 c ; reset = h (unless otherwise specified) min typ max 5 . diagnostic functions open load detection voltage v ds(ol) v s - 2.5 v s - 2 v s - 1.3 v output pull down current i pd(ol) 50 90 150 a fault delay time t d(fault) 50 110 200 s short to gro und detection voltage v ds(shg) v s ? 3.3 v s - 2.9 v s - 2.5 v short to ground detection current i shg - 50 - 100 - 150 a 6 . spi - timing serial clock frequency (depending on so load) f sck dc -- 5 mhz serial clock period (1/fclk) t p(sck) 200 -- -- ns serial cl ock high time t sckh 50 -- -- ns serial clock low time t sckl 50 -- -- ns enable lead time (falling edge of cs to rising edge of clk ) t lead 250 -- -- ns enable lag time (falling edge of clk to rising edge of cs ) t lag 250 --- -- ns data setup time (required time si to falling of clk) t su 20 -- -- ns data hold time (falling edge of clk to si) t h 20 -- -- ns disable time @ c l = 50 pf 8 t dis -- -- 150 ns transfer delay time 7 ( cs high time between two acce sses) t dt 200 -- -- ns data valid time c l = 50 pf c l = 100 pf 8 c l = 220 pf 8 t valid -- -- -- -- -- -- 110 120 150 ns 7 this time is necessary between two write accesses. to get the correct diagnostic information, the transfer delay time has to be extended to the maximum fault delay time t d(fault)max = 200s. 8 this parameter will not be tested but guaranteed by design
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 6 functional description the tle 6220 gp is an quad - low - side power switch which provides a serial peripheral inte r- face (spi) to con trol the 4 power dmos switches, as well as diagnostic feedback. the power transistors are protected against short to v bb , overload, overtemperature and against ove r- voltage by an active zener clamp. the diagnostic logic recognises a fault condition which c an be read out via the serial diagno s- tic output (so). circuit description power transistor protection functions 9 ) each of the four output stages has its own zener clamp, which causes a voltage limitation at the power transistor when solenoid loads are switched off. the outputs are provided with a current limitation set to a minimum of 3 a. the continuous current for each channel is 1a (all channels on; depending on cooling). each output is protected by embedded protection functions. in the event of an overload or short to supply, the current is internally limited and the corresponding bit combination is set (early warning). if this operation leads to an overtemperature condition, a second protection level (about 170 c) will change the output into a lo w duty cycle pwm (selective thermal shu t- down with restart) to prevent critical chip temperatures. spi signal description cs - chip select. the system microcontroller selects the tle 6220 gp by means of the cs pin. whe never the pin is in a logic low state, data can be transferred from the c and vice versa. cs high to low transition: - diagnostic status information is transferred from the power outputs into the shift regi ster. - serial input data can be clocked in from then on. - so changes from high impedance state to logic high or low state corresponding to the so bits. cs low to high transition: - transfer of si bits from shift register into output buffers - reset of diagnosis register. to avoid any false clocking the serial clock input pin sclk should be logic low state during high to low transition of cs . when cs is in a logi c high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. 9 ) the integrated protection functions prevent an ic destruction under fault conditions and may not be used in normal operation or perm a nently .
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 7 sclk - serial clock. the system clock pin clocks the internal shift register of the tle 6220 gp. the serial input (si) accepts data into the input shift register on the falling edge of sclk while the serial output (so) shifts diagnostic information out of the shift register on the rising edge of serial clock. it is essential that the sclk pin is in a logic low state whenever chip select cs makes any transition. si - serial input. serial data bits are shifted in at this pin, the most significant bit first. si info r- mation is read in on the falling edge of sclk. input data is latched in the shift register and then transferred to the c ontrol buffer of the output stages. the input data consists of one byte, made up of four control bits and four data bits. the co n- trol word is used to program the device, to operate it in a certain mode as well as providing dia g nostic information (see page 11 ). the four data bits contain the input information for the four channels, and are high active. so - serial output. diagnostic data bits are shifted out serially at this pin, the most significant bit first. so is in a high impedance s tate until the cs pin goes to a logic low state. new dia g- nostic data will appear at the so pin following the rising edge of sclk. reset - reset pin. if the reset pin is in a logic low state, it clears the spi shift registe r and switches all outputs off. an internal pull - up structure is provided on chip. as long as the r e- set pin is low the device is in low quiescent current mode and the supply current is reduced to typ. 20a. output stage control the four outputs of the t le 6220 gp can either be controlled in parallel (in1...in4), or via the s e rial peripheral interface (spi). parallel control a boolean operation (either and or or) is performed on each of the parallel inputs and r e- spective spi data bits, in order to deter mine the states of the respective outputs. the type of boolean operation performed is programmed via the serial interface. the parallel inputs are high or low active depending on the prg pin. if the parallel input pins are not connected (independent of hig h or low activity) it is guaranteed that the outputs 1 to 4 are switched off. prg pin itself is internally pulled up when it is not connected. prg - program pin. prg = high ( v s ): parallel inputs channel 1 to 4 are high active prg = low (gnd): parallel inputs channel 1 to 4 are low active.
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 8 serial control of the outputs: spi protocol each output is independently controlled by an output latch and a common reset line, which di s ables all four outputs. the serial input (si) is read on the falling edge of the serial clock. a logic high input 'data bit' turns the respective output channel on, a logic low 'data bit' turns it off. cs must be low whilst shifting all the serial data into the device. a low - to - high transition of cs tran s fers the serial data input bits to the output control buffer. as mentioned above, the serial input byte consists of a 4 bit control word and a 4 bit data word. via the control word, the specific mode of the device is programmable. msb lsb 3 2 1 3 2 1 bits data bits control dddd cccc : serial input byte five specific control words are recognised, having the following functions: no. serial input byte function 1 llll xxxx only 'full diagnosis' performed. no change to ou tput states. 2 hhll xxxx state of four parallel inputs and '1 - bit diagnosis' outputted. 3 hlhl xxxx echo - function of spi; si direct connected to so 4 llhh dddd in1...4 and serial data bits 'or'ed. 'full diagnosis' performed. 5 hhhh dddd in1...4 and serial data bits 'and'ed. 'full diagnosis' performed. note: 'x' means 'don't care', because this bit will be ignored 'd' represents the data bit, either being h (=on) or l (=off) 1. llll xxxx - diagnosis only by clocking in this control byte, it is possible to get pure diagnostic information (two bits per channel) in accordance with figure 1 (page 11 ). the data bits are ignored, so that the state of the outputs are not influenced. this command is only active once unless the next control co m- mand is again "diagnosis only". 2. hhll xxxx - reading back of input, and ?1 - bit diagnosis? if the tle 6220 gp is used as bare die in a hybrid application, it is necessary to know if proper connections exist between the c - port and parallel inputs. by entering ?hhll? as the control word, the first four bits of the so give the state of the parallel inputs, depending on the c signals. by comparing the four in - bits with the corresponding c - port signal, th e nece s- sary connection between the c and the tle 6220 can be verified - i.e. ?read back of the i n- puts?. the second 4 - bit word fed out at the serial output contains ?1 - bit? fault information of the ou t- puts ( h = no fault, l = fault ). in the expression gi ven below for the output byte, ?fx? is the fault bit for channel x. msb lsb in4 in3 in2 in1 f4 f3 f2 f1 : serial output byte
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 9 si h h l l x x x x so h h h h h h h h cs cs si h h h h l h h l so in4 in3 in2 in1 f4 f3 f2 f1 si command : no change of the output state; reading back of inputs and 1bit diagnosis so diagnosis : no fault, normal function cs si h h h h l l l l so h h h h h h h h si command : and-operation; ch1 and 4 off, ch2 and 3 on. so diagnosis : state of four parallel inputs and 1 bit diagnosis performed si command : and-operation and all channels off. so diagnosis : no fault, normal function 3. hlhl xxxx - echo - function of spi to check the proper function of the seri al interface the tle 6220 gp provides a "spi echo function". by entering hlhl as control word, si and so are connected during the next cs p e riod. by comparing the bits clocked in with the serial output bits, the proper function of the spi interface can be verified. this internal loop is only closed once (for one cs period). si h l h l x x x x so h h h h l h h h cs cs si so si command : no change of the output states; echo function of spi so diagnosis : open load condition at channel 2, other channels ok. si word echo-function of spi , i.e. si directly connected to so. si information will be accepted during this cycle and the outputs set accordingly after chip select rising edge 4. llhh dddd - or operation, and ?full diagnosis? with llhh as the control word, each of the input signals in1...in4 are 'or'ed with the corr e- sponding data bits (dddd). 3 1 output driver in 1...4 serial input, data bits 0...3 this or operation enables the serial interface to switch the channel on, even though the co r- responding parallel input might be in the off state. t spi priority for on - state also pa rallel control of the outputs is possible without an spi input.
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 10 the or - function is the default boolean operation if the device restarts after a reset, or when the supply voltage is switched on for the first time. if the or operation is programmed it is l atched until it is overwritten by the and operation. 5. hhhh dddd - and operation, and ?full diagnosis? with hhhh as the control word, each of the input signals in1...in4 are 'and'ed with the co r- responding data bits (dddd). & output driver in 1...4 serial input, data bits 0...3 the and operation implies that the output can be switched off by the spi data bit input, even if the corresponding parallel input is in the on state. t spi priority for off - state this also implies that the serial input data bit can only switch the output chan nel on if the co r- responding parallel input is in the on state. if the and operation is programmed it is latched until it is overwritten by the or operation. control words beside no. 1 - 5 all control words except those for diag only, read back of inputs, spi echo, will be accepted as an or or an and command with valid data bits depending on the boolean operation which was programmed before. example 1: llhh hllh: or operation between parallel inputs and data bits, i.e channel 1 and 4 will be switched on. the next command is now: lhhh hhlh lhhh as command word has no special meaning but it will be accepted as an or operation and the data bits will be ored with the inputs and the outputs 1,3 and 4 will be switched on. see above: 'if the or operation is prog rammed it is latched until it is overwritten by the and o p eration.' example 2: hhhh llhl means: data bits will be anded with the parallel inputs and the outputs switch a c cordingly. then hllh hhlh is clocked in: and was latched by the command before and i s now valid again by using the hllh command word. so the data bits will be accepted and again anded with the parallel input signals. see above: 'if the and operation is programmed it is latched until it is overwritten by the or o p eration.'
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 11 diagnostics fault - fault pin. there is a general fault pin (open drain) which shows a high to low trans i- tion as soon as an error occurs for any one of the four channels. this fault indication can be used to generate a c interrupt. th erefore a ?diagnosis? interrupt routine need only be called after this fault indication. this saves processor time compared to a cyclic reading of the so i n formation. as soon as a fault occurs, the fault information is latched into the diagnosis register. a new e r ror will over - write the old error report. serial data out pin (so) is in a high impedance state when cs is high. if cs receives a low signal, all diagnosis bits can be shifted out serially. the rising edge of cs will reset all error registers. full diagnosis for full diagnosis there are two diagnostic bits per channel configured as shown in figure 1. normal function: the bit combination hh indicates that there is no fault condition, i.e. normal function. overload, short circuit to battery (scb) or overtemperature: hl is set when the current limitation gets active, i.e. there is a overload, short to supply or overtemp erature condition. open load: an open load condition is detected when the drain voltage decreases below 3 v (typ.). lh bit combination is set. short circuit to gnd: if a drain to ground short circuit exists and the drain to ground current e x ceeds 100 a, short to ground is detected and the ll bit combination is set. a definite distinction between open load and short to ground is guaranteed by design. the standard way of obtaining diagnostic information is as follows: clock in serial information into si p in and wait approximately 150 s to allow the outputs to settle. clock in the identical serial information once again - during this process the data co m- ing out at so contains the bit combinations representing the diagnosis conditions as d e- scribed in fi g ure 1. diagnostic serial out (so) hh normal function hl overload, shorted load or overtemperature lh open load ll shorted to ground ch.4 ch.3 ch.2 ch.1 7 6 5 4 3 2 1 0 figure 1: two bits per channel diagnostic feedback
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 12 timing diagrams figure 2: serial interface figure 3: input timing diagram figure 4: so valid time waveforms enable and disable time wav e forms data bits 6 7 4 4 4 4 8 4 4 4 4 control bits 6 7 4 4 4 4 8 4 4 4 4 cs sclk si old new 7 6 5 4 3 2 1 0 so 7 6 5 4 3 2 1 0 msb lsb outputs t lead t sckh 0.2v s t lag t h t sckl 0.2 v s t su 0.7v s 0.2v s cs sclk si 0.7vs t dt 0.7vs t valid sclk cs so t dis 0.2 v s so 0.7 v s 0.7 v s 0.2 v s so 0.7 v s 0.2 v s
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 13 figure 5: power outputs application circuit t t t on t off 80% v ds v in 20% out1 out2 out4 tle 6220 gp si so clk cs vs vs reset gnd v bb clk mtsr mrst p xy c e.g. c166 in1 in2 in3 in4 fault prg 10k
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 14 typical electrical characteristics drain - source on - resistance r ds(on) = f (t j ) ; v s = 5v output clamping voltage v ds(az) = f (t j ) ; v s = 5v figure 6 : typical on resistance versus junction - temper a ture channel 1 - 4 fi gure 7 : typical clamp voltage versus junction - temperature channel 1 - 4 typical drain- source on-resistance 0,23 0,28 0,33 0,38 0,43 0,48 0,53 0,58 -50 -25 0 25 50 75 100 125 150 175 tj[c] rds(on) [ohm] channel 1-4 typical clamping voltage 48 49 50 51 52 53 54 55 -50 -25 0 25 50 75 100 125 150 175 tj[c] vds (az) [v] channel 1-4
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 15 parallel spi configuration engine management application tle 6230 gp in combination with tle 6240 gp (16 - fold switch) for relays and general purpose loads and tle 6220 gp (quad switch) to drive the injector valves. this arrangement covers the numerous loads to be driven in a modern engine management/powertrain system. from 28 channels in sum 16 can be controlled direct in parallel for pwm applications. daisy chain application tle 6220 gp 4 si clk so 4 si clk so cs cs mtsr mrst clk p x.y p x.1-4 p x.y p x.1-4 c c167 4 pwm channels 4 pwm channels cs injector 1 injector 2 injector 3 injector 4 tle 6220 gp quad tle 6230 gp octal 8 si clk so cs 8 pwm channels tle 6240 gp 16-fold p x.y p x.1-8 cs si clk so tle 6220 gp quad cs si clk so tle 6220 gp quad cs si clk so tle 6220 gp quad cs px.1 px.2 c mtsr mrst
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 16 package and ordering code (all dimensions in mm) p g - ds o - 20 tle 6220 gp 0 . 1 8 1 . 3 1.2 -0.3 1 5 . 9 + / - 0 . 1 5 a 2.8 8 8 8 6.3 1 1 + / - 0 . 1 5 1 ) 1 4 . 2 + / - 0 . 3 1 10 11 20 p i n 1 i n d e x m a r k i n g 1 x 45 13.7 -0.2 9 x = 1 1 . 4 3 1 . 2 7 1 . 2 7 0.25 a m 0 . 4 + 0 . 1 3 3 . 2 + / - 0 . 1 5 . 9 + / - 0 . 1 1 5 . 7 4 + / - 0 . 1
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 17 green product (rohs compliant) to meet the world - wide customer requirements for environmentally friendly products and to be co m- pl i ant with government regulations the device is available as a gr een product. green products are rohs - compliant (i.e pb - free finish on leads and suitable for pb - free soldering according to ipc/jedec j - std - 020).
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 18 revision hi story version date changes v2.1 - > v2.2 18.11.2009 package changed to pg - dso - 2 0 ordering code re moved v2.0 - > v2.1 20.04.2007 ordering code removed layout changes c orrect green pac k age name implemented p - dso - 20 - 12 pg - dso - 20 - 26 v1.1 - > v2.0 20.05.2003 changes to green product version: - aec, rohs logo and feature list co n tent added - package name p - dso - > pgdso - change history added - disclaimer re - newed v1.1 28.08.2007 initial version of ?grey? product
data sheet tle 6220 gp v2.2 page 200 9 - 11 - 18 19 edition 2007 - 04 - 17 published by infineon technologies ag 81726 munich, germany ? 11/19/09 infineon technologies a g all rights reserved. legal disclaimer the information given in this document shall in no event be regarded as a guarantee of conditions or characteri s- tics. with respect to any examples or hints given herein, any typical values stated herein and/or any in fo r mation regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabil i- ties of any kind, including without limitation, warranties of non - infringement of intellectual property rights of any third party. i nformation for further information on technology, delivery terms and conditions and prices, please contact the nearest i n- fineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies components may be used in life - support devices or systems only with the express wri t ten approval of infineon technologies, if a failure of such components can reasonably be expected to cause the fai l ure of that life - support device or system or to affect the safety or effectiveness of that device or system. life su p port devices or systems are intended to be implanted in the human body or to s upport and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other pe r- sons may be endangered.

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